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Add SiFive InclusiveCache #128

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merged 3 commits into from Jul 3, 2019
Merged

Add SiFive InclusiveCache #128

merged 3 commits into from Jul 3, 2019

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zhemao
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@zhemao zhemao commented Jul 2, 2019

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@zhemao zhemao requested a review from abejgonzalez July 2, 2019 22:44
abejgonzalez
abejgonzalez approved these changes Jul 3, 2019
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LGTM

colinschmidt
colinschmidt approved these changes Jul 3, 2019
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LGTM but I'd like to add a more complex config to CI (just needs to build).

generators/example/src/main/scala/Configs.scala Show resolved Hide resolved
@sequencer sequencer mentioned this pull request Jul 3, 2019
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@abejgonzalez
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Merging for now with knowing that BOOM is for some reason broken on this bump. Will address later.

@abejgonzalez abejgonzalez merged commit 48b2d6b into dev Jul 3, 2019
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I think we should file issues about things that we will address later. I filed one about my L2 config complaint, and you should file one about fixing boom with the l2, IMO. Otherwise its very easy to lose track of things.

@davidbiancolin
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Issues or it never happened.

@abejgonzalez
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Thanks to @jerryz123 this: riscv-boom/riscv-boom#315 should address the issue.

@colinschmidt colinschmidt deleted the dev-L2 branch August 20, 2019 16:43
jerryz123 added a commit that referenced this pull request Apr 19, 2023
@jerryz123
Merge pull request #128 from ucb-bar/fesvr-init-writes
89b9d66 
Test chip features
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@abejgonzalez abejgonzalez abejgonzalez approved these changes

@colinschmidt colinschmidt colinschmidt approved these changes

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@zhemao @abejgonzalez @colinschmidt @davidbiancolin